Skip to content
OpenCDD
t_PHLv2rev 42015-03-13IEC 60748-2 (II.1.4.7) (1985)

HIGH to LOW propagation delay time

0112/2///61360_4#AAE233

time required for a transition from a logic HIGH level to a logic LOW level to propagate from the input terminal to the output terminal of a digital function of an integrated circuit, at specified conditions

Used by classes
2
property
Code
AAE233
Data type
LEVEL(MIN,MAX,TYP) OF REAL_MEASURE_TYPE
Unit
UAA972 UAA972
Used by classes (2)

Version history6#

  1. Current rev 04
    17 Aug 2015 · 15:40 UTC by BATCH 00000917
    View on cdd.iec.ch ↗
  2. superseded rev 03
    23 Jul 2015 · 11:08 UTC by BATCH 00000907
    ↓ Version JSON
    View on cdd.iec.ch ↗
  3. superseded rev 02
    22 Jul 2015 · 14:21 UTC by BATCH 00000904
    ↓ Version JSON
    View on cdd.iec.ch ↗
  4. superseded rev 01
    19 Dec 2014 · 13:10 UTC by BATCH 00000881
    ↓ Version JSON
    View on cdd.iec.ch ↗
  5. superseded rev 02
    30 May 2012 · 15:03 UTC by BATCH 00000788
    ↓ Version JSON
    View on cdd.iec.ch ↗
  6. superseded rev 01
    30 May 2012 · 14:53 UTC by BATCH 00000787
    ↓ Version JSON
    View on cdd.iec.ch ↗

IEC CDD records every published revision of each entity — version number, status, timestamp, and the change request that introduced it. OpenCDD captures the full chain of custody from cdd.iec.ch; the entry marked Current is the one rendered on this page.

Metadata#

Source document
IEC 60748-2 (II.1.4.7) (1985)
Version
2
Revision
4
Status
Standard
Publisher
IEC
Published in
IEC 61360-4
Responsible committee
SC3D
Dates
  • Original: 1996-08-01
  • Current version: 2015-03-13
  • Current revision: 2015-08-17